This invention relates to a transceiver and, more particularly, to a transmitting apparatus for dividing transmit data from each of a plurality of terminals into prescribed lengths of time, applying encoding processing to the divided data, multiplexing the encoded data thus obtained and transmitting the multiplexed signal, and to a receiving apparatus for demultiplexing multiplexed encoded data that has been received, applying decoding processing and sending the decoded data obtained to prescribed terminals.
In a CDMA (Code Division Multiple Access) mobile communications system, a base station spread-spectrum modulates control information and user information of multiple users using respective ones of different spreading code sequences, multiplexes and transmits the information, and each of a number of mobile stations transmits and receives information upon spreading and de-spreading the information using spreading codes specified by the base station.
FIG. 17 is a block diagram showing the structure of a mobile station according to the prior art. During reception, a radio unit 1 subjects a high-frequency signal received from an antenna ANTR to a frequency conversion (RFxe2x86x92IF conversion) to obtain a baseband signal. A quadrature detector 2 subjects the baseband signal to quadrature detection and outputs in-phase component (I component) data and quadrature component (Q component) data. A/D converters 3a, 3b convert the I-component and Q-component signals, respectively, to digital signals, and the digital signals enters a search 4 and respective ones of fingers 51-54. If a direct sequence signal (DS signal) that has experienced multipath effects enters, the searcher 4 executes autocorrelation processing using a matched filter (not shown), detects multipaths and inputs, to the fingers 51-54, despreading-start timing data and delay-time adjustment data for the various paths.
Each of the fingers 51-54 has a despreader/delay-time adjustment unit 5a for performing dump integration by subjecting a direct wave or a delayed wave that arrives via a prescribed path to despread processing using a code identical with the spreading code, and for subsequently applying delay processing that conforms to the path and outputting a pilot signal (reference signal) and information signal; a phase compensator (channel estimation unit) 5b for averaging voltages of the I and Q components of the pilot signal over a prescribed number of slots and outputting channel estimation signals It, Qt; and a synchronous detector 5c for restoring the phases of despread information signals Ixe2x80x2, Qxe2x80x2 to the original phases based upon a phase difference xcex8 between a pilot signal contained in a receive signal and an already existing pilot signal. More specifically, the channel estimation signals It, Qt are cosine and sine components of the phase difference xcex8, and therefore the synchronous detector 5c demodulates the receive information signal (I,Q) (performs synchronous detection) by applying phase rotation processing to the receive information signal (Ixe2x80x2,Qxe2x80x2) in accordance with the following equation using the channel estimation signal (It,Qt):       (                            I                                      Q                      )    =            (                                    It                                Qt                                                              -              Qt                                            It                              )        ⁢          (                                                  I              xe2x80x2                                                                          Q              xe2x80x2                                          )      
A rake combiner 6 combines signals output from the fingers 51-54 and outputs the combined to a decoding processor (channel decoder) 7.
The decoding processor 7 subjects the input signal to error correction processing, decodes the original transmit data and stores the decoded data in a receive buffer 8. A data selector 9 inputs the decoded data, which has been stored in the receiver buffer 8, to prescribed terminal equipment (TE). Examples of the terminal equipment TE are a telephone 10, a facsimile transceiver 11, a personal computer 12 and an ISDN terminal 13. The telephone 10 is constituted by a voice codec 10a, a speaker 10b and a microphone 10c and is permanently connected to the data selector 9. The facsimile transceiver 11, personal computer 12 and ISDN terminal 13, however, are connected to the data selector 9 selective via an adapter 14xe2x80x2.
During transmission, the data selector 9 stores transmit data, which enters from an originating terminal, in a transmit buffer 14, and an encoding processor (channel encoder) 15 subjects the transmit data to encoding processing and outputs the encoded data as in-phase component data. A control signal generator 16 outputs control data, such as a pilot signal, as quadrature-component data at a fixed symbol speed. A QPSK spreader 17 subjects the entered in-phase component (I-channel component) and quadrature-phase component (Q-channel component) to spread-spectrum modulation using a prescribed spreading code, converts the digital modulated signals to analog signals and inputs the analog signals to a QPSK quadrature modulator 18. The latter subjects the I-channel and Q-channel signals to QPSK quadrature modulation, and a radio transmitter 19 frequency-converts (IFxe2x86x92RF) the baseband signal from the quadrature modulator 18 to a high-frequency signal, performs high-frequency amplification and transmits the amplified signal from an antenna ANTT.
FIG. 18 is a diagram useful in describing the frame format of an upstream signal from a mobile station to a base station. One frame has a length of 10 ms and is composed of 15 slots S0 to S14. User data is mapped to the I channel of QPSK modulation and control data is mapped to the Q channel of QPSK modulation. The number n of bits in each slot in the I channel for user data varies in dependence upon symbol speed. Each slot in the Q channel for control data is composed of ten bits and the symbol speed is a constant 15 Kbps.
FIG. 19 is a diagram useful in describing the frame format and slot arrangement of a downstream signal from a base station to a mobile station. One frame has a length of 10 ms and is composed of 15 slots S0 to S14. Each slot contains a mixture of user data Data 1, Data 2 and control data TPC, TFCI, PILOT. The data in each slot is distributed in turns to the I channel and Q channel of QPSK quadrature modulation one bit at a time, after which spread-spectrum modulation and quadrature modulation is applied, frequency conversion is carried out and the resultant signal is transmitted to the mobile station.
Encoding Processing According to the Prior Art
In order to apply channel coding to continuous data sent from terminal equipment TE or the like at the time of transmission in the conventional mobile radio unit described above, it is required that the continuous data be delimited into prescribed processing units (10-ms intervals or the like) and subjected to channel coding in the prescribed units of processing. For example, if 64-Kbps data is delimited in increments of 10 ms and encoding processing is applied every 640 bits, operation will be as shown in FIG. 20. Specifically, the terminal equipment TE sends data continuously but the mobile radio unit delimits the input data into units of processing (10-ms increments) and applies channel coding to data that has been delimited in 10-ms increments.
In this case, as shown in FIG. 21, the speed of data sent from the terminal equipment TE and processing speed on the encoding side generally have different clocks. In a mobile radio unit, speed up to the writing of data to the transmit buffer 14 depends upon speed on the side of the terminal equipment TE, but speed following the read-out of data from the transmit buffer 14 and the application of encoding processing is made high in order to minimize processing delay. If voice is taken as an example, the problem of echo occurs when the processing delay is too long. Accordingly, encoding processing is executed at high speed to minimize processing delay up to the wireless transmission of the voice data. In the case shown in FIG. 21, data is input from the terminal equipment TE at a bit rate of 64 Kbps, and the encoding processor 15 reads the data from the transmit buffer 14 at a frequency of 20 MHz and encodes the data.
Two-bank System
In the case of continuous data (see FIG. 20), a two-bank system is available as a method of implementing the processing of continuous data. The two-bank system involves (1) constructing the buffer 14 from two banks, as shown in FIG. 22; (2) writing data alternately to a bank (BANK 1) 141 on the write side and to a bank (BANK 2) 142 on the read side at 10-ms time intervals (see FIG. 23); and (3) writing data to one bank and reading data out of the other bank simultaneously. In accordance with the two-bank system, encoding processing can be executed while data continuity is maintained.
Decoding Processing when Multiple Items of Terminal Equipment TE are Connected
There are instances where multiple items of terminal equipment TE are connected to a mobile radio unit (see FIG. 17). Even if multiple items of terminal equipment TE are connected, however, it is unnecessary in the prior art to provide a transmit buffer separately for each individual item of terminal equipment TE; the transmit buffer is shared by the terminal equipment. The reason for this is that the conventional mobile unit does not perform communication using multiple items of terminal equipment TE simultaneously. This means that it will suffice to provide, as the transmit and receive buffers, memories having a capacity conforming to the terminal equipment TE having the highest transmission speed. FIG. 24 illustrates a prior-art arrangement that shares the transmit buffer 14. In FIG. 24, terminals TE1, TE2, TE3 and TE4 send 640-, 9600-, 128- and 256-bit data, respectively, every 10 ms. These terminals, however, are not utilized simultaneously. Accordingly, the transmit buffer 14 provided is a 9600-bit buffer conforming to the terminal equipment TE of maximum speed. When the other items of terminal equipment (other services) are activated, the transmit buffer 14 is shared.
In accordance with a scheme proposed by a standardization project 3GPP (3rd Generation Partnership Project) for next-generation W-CDMA, it is necessary to so arrange it that data can be sent and received upon executing encoding processing at arbitrary time intervals of 10 ms, 20 ms, 40 ms and 80 ms. It is also necessary to so arrange it that multiple services can be connected simultaneously. To accomplish this, the arrangement of FIG. 24 cannot be utilized. If a buffer is provided for every item of terminal equipment, on the other hand, a very large number of memories will be required. The problems encountered in realizing the scheme proposed by the 3GPP will be discussed centering on the transmitting side. In the description that follows, it will be assumed that the speeds of the terminals are identical.
Viterbi code or turbo code used in error correction is such that the larger the number of encoded bits, the more error correction capability can be improved. In channel coding proposed as by the 3GPP, therefore, data for which improved error correction is sought requires that encoding processing be executed in time-length units of 20 ms, 40 ms and 80 ms. FIG. 25 shows an example in which user data sent from terminal equipment TE is input to the encoding processor 15 in amounts of 40 ms each.
Further, with channel coding proposed by the 3GPP, etc., it is possible to connect multiple terminals TE1, TE2, TE3, TE4 . . . simultaneously and it is necessary to take a multiplex buffer into consideration from the viewpoint of service. However, if buffers 1411, 1412, 1413, 1414, . . . are provided for respective ones of the terminals TE1, TE2, TE3, TE4 . . . , a large number of memories will be required. With this arrangement, moreover, it is necessary to increase the number of transmit buffers whenever an item of terminal equipment TE is added on. Such a memory configuration has no flexibility. For this reason, consideration has been given to constructing the transmit buffer 14 physically from a single memory and allowing the each of the terminals TE to use the memory vacancies the required number at a time, thereby enabling the capacity of the memory to be reduced. To achieve this, it is necessary to (1) manage free space of the memory, (2) assign free space to a terminal as required and (3) control data read/write on a per-terminal basis.
FIG. 27 illustrates an example in which such read/write control is implemented. Here a processor 21 manages the free space of transmit buffer 14, designates the write addresses of data from the terminals TE1, TE2, TE3 . . . in a hard macro 22 for data write, and designates read addresses in an encoding hard macro (hard macro for data read) 23. In accordance with these designations, the hard macro 22 writes the service data of each terminal to the designated area of the transmit buffer 14 and the encoding hard macro 23 reads the data of each terminal out of the designated area of transmit buffer 14 and inputs the data to the encoding processor 15.
In the arrangement of FIG. 27, the operations for writing data to the transmit buffer 14 and for reading data out of the transmit buffer 14 are implemented by the hard macros 22, 23 in order to alleviate the load on the processor 21. It is required that the spaces written and read by the hard macros 22, 23 at such time be continuous. The reason for this is as follows, taking the read operation as an example: The hard macro 23 does not possess an intelligent function; it has only a function for reading out data continuously upon designating (1) the starting read-out address and number of items of data to be read out or (2) the starting read-out address and the final read-out address. Similarly, on the write side, it is necessary to so arrange it that data will be written to continuous space.
However, there are instances where a service provided by a terminal is added on or deleted at the volition of the user. FIG. 28 is a diagram useful in describing the status of a buffer, which depends upon the addition/deletion of services. As shown in (A) of FIG. 28, data of services 1, 2, 3 provided by terminals TE1, TE2, TE3 is stored in areas 1411, 1412, 1413, respectively, of the buffer 14 and is processed at the required time intervals. If service 2 is deleted at a certain time under these conditions, as by detaching terminal TE2 from its adapter, a hole is produced in the content of the buffer 14, as shown in (B) of FIG. 28. Consider a case where a new service 4 is added on in the presence of such a hole, as illustrated in (C) of FIG. 28. Though the buffer 14 has enough free space to store the data of the new service 4, there is no space for physically buffering data continuously. Consequently, it is necessary to split the data of service 4 into two spaces and then write the data to the buffer. As mentioned above, however, it is not possible for the hard macro 22 to write data to areas that are discontinuous. Even if the data is written, moreover, the encoding hard macro 23 cannot read out data unless the data is contained in space that is continuous. This means that writing the data in the first place is meaningless. In other words, with the arrangement shown in FIG. 27, the problem which arises is that there are situations where the adding on of new services cannot be supported.
Further, with management that assigns an area of the minimum necessary size to each service, as shown in FIG. 27, a problem which arises is a complicated bank switching operation. For example, assume that terminal TE1 executes a service for which the length of encoding time is 40 ms, terminal TE2 a service for which the length of encoding time is 10 ms and terminal TE3 a service for which the length of encoding time is 20 ms. In such case it will be necessary to design the hard macros 22, 23 in such a manner that bank switching can be carried out at the respective time intervals, as depicted in FIG. 29. When addition/deletion of a service is taken into consideration, the hard macros 22, 23 must be so adapted that bank switching can be performed at any timing. This cannot be achieved with a simple arrangement. Further, if service addition/deletion occurs, as shown in FIG. 28, it is necessary to perform address management in such a manner that will not impede the switching of each bank and that will not cause holes to appear in the buffer memory. The problem that arises is complicated address management.
Thus, in a case where a single memory contains a mixture of data representing services for which the lengths of encoding time are 10 ms, 20 ms, 40 ms and 80 ms, etc., bank switching and address management become complex and so does the structure of the hard macros, meaning that the original advantages of the hard macros are lost.
In light of the problems set forth above, arrangements will be described in which address management and bank switching can be performed in simple fashion in a case where a plurality of terminals that provide services for which the lengths of encoding time are 10 ms, 20 ms, 40 ms and 80 ms are connected.
FIG. 30 illustrates a first example of such an arrangement. This shows an example (of one bank""s worth of memory) in which services S1 to S8 of respective terminals are provided with enough memory for the maximum length of encoding time (=80 ms). If the maximum bit rate from each of the terminals TE1 to TE8 is 64 Kbps, 640xc3x978 bits of memory are provided for each of the services S1 to S8. In accordance with such an arrangement, no problem whatsoever arises even in a case where the services S1 to S8 are encoded at arbitrary lengths of encoding time. Further, support is possible without any problem even in terms of addition/deletion of services.
FIG. 31 illustrates a second example of such an arrangement. This shows an example in which two bank""s worth of memory are provided, each memory bank storing 80, 40, 20 and 10 millisecond""s worth of data, in terms of lengths of encoding time, for the respective services S1 to S4. One bank has 640xc3x978 bits of memory for service S1, 640xc3x974 bits of memory for service S2, 640xc3x972 bits of memory for service S3 and 640xc3x971 bits of memory for service S4. In accordance with this arrangement, memory is constructed for per length of encoding time. As a result, data having different lengths of encoding time is not mixed in one memory and both address management and bank switching can be performed in simple fashion.
Since the first memory arrangement of FIG. 30 necessitates two bank""s worth of memory, the total amount of memory required is (amount of data for 80 ms)xc3x97(number of services)xc3x97(number of banks). The result is a very large memory capacity. Such a memory arrangement is not suited to a mobile radio station that requires small size and low cost.
With the second memory arrangement of FIG. 31, the amount of memory can be reduced over that of the first memory arrangement. Since two bank""s worth of memory is required, however, the memory reducing effect is unsatisfactory. Further, with the second memory arrangement, two or more services for each of which the length of encoding time is 80 ms cannot be connected, and neither can three or more services for each which the length of encoding time is 40 ms.
The foregoing has been described centering on the construction of the transmit buffer. However, the same problems hold true for the receive buffer as well.
Accordingly, an object of the present invention is to so arrange it that data having different lengths of encoding time will not be mixed in a buffer memory, address management and bank switching can be performed in simple fashion and the amount of necessary memory can be reduced.
Another object of the present invention is to so arrange it that a service having any length of encoding time can be connected using a small amount of memory.
A first aspect of the present invention relates to a transmitting apparatus for storing transmit data, which relates to respective ones of N-number of 1st to Nth services, in lengths equivalent to a multiple ni (i=1, 2, . . . , N) of a reference time length T, reading out the stored transmit data nixc2x7T at a time, encoding each read item of transmit data of length nixc2x7T, and transmitting the encoded data. The transmitting apparatus comprises: (1) a transmit buffer having a first storage unit for storing, on a per-service basis, transmit data of length nixc2x7T, and a second storage unit for storing, on a per-service basis, transmit data of the reference time length T; (2) an encoding processor for encoding and then outputting transmit data of each service of length nixc2x7T (i=1, 2, . . . , N); (3) a controller which, on a per-service basis, stores the transmit data of length nixc2x7T in the transmit buffer continuously, reference time length T at a time, at low speed; then, after storage of this data, reads already stored transmit data of length nixc2x7T out of the transmit buffer at high speed in parallel with storage of succeeding transmit data of reference time length T in the transmit buffer; then subsequently performs, in parallel fashion, low-speed continuous storage of transmit data of length nixc2x7T and high-speed intermittent read-out of already stored transmit data of length nixc2x7T; and inputs, to the encoding processor, the transmit data that has been read out; (4) a multiplexer for multiplexing data obtained by the encoding processing of transmit data of length nixc2x7T of each service; and (5) a transmitter for transmitting the multiplexed data.
A second aspect of the present invention relates to a receiving apparatus for demultiplexing encoded data of N-number of 1st to Nth services that have been multiplexed and sent to the receiving apparatus, decoding demultiplexed encoded data of each ith service (i=1, 2, . . . , N), storing the decoded data for lengths of time that are a multiple ni (i=1, 2, . . . , N) of a reference time length T, reading out stored transmit data n1xc2x7T at a time, transmitting the data to a terminal, and performing, in parallel, storage and read-out of decoded data on a per-service basis. The receiving apparatus comprises: (1) a demultiplexer for demultiplexing encoded data of N-number of services from received data; (2) a decoding processor for decoding original data of length nixc2x7T from encoded data of each service; (3) a receive buffer having a first storage unit for storing, on a per-service basis, decoded data of length nixc2x7T, and a second storage unit for storing, on a per-service basis, decoded data of the reference time length T; and (4) a controller which, on a per-service basis, intermittently stores decoded data of length nixc2x7T in the receive buffer at high speed; of the stored decoded data of length nixc2x7T, reads out decoded data of length (nixe2x88x921)xc2x7T continuously, reference time length T at a time, at low speed; stores succeeding transmit data of length nixc2x7T in the receive buffer at high speed in parallel with read-out of final decoded data of reference time length T; then subsequently performs, in parallel fashion, low-speed continuous read-out of transmit data of length nixc2x7T and high-speed intermittent storage of transmit data of length nixc2x7T.
In accordance with the transmitting apparatus and receiving apparatus according to the present invention, it suffices merely to provide, as a second bank, a storage area of small capacity for storing, for each service, data of the reference length of time T. This makes it possible to reduce the overall amount of memory. Further, since the buffer memory does not store a mixture of data having different lengths of encoding time, address management and bank switching can be performed in simple fashion. Further, if an arrangement is adopted in which transmit data of the maximum length of encoding time is stored, on a per-service basis, in the first storage unit serving as the first bank, a service having any length of encoding type can be connected using an amount of memory that is comparatively small.
Other features and advantages of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof.